The present invention relates to a nonvolatile, integrated-circuit memory array such as a flash erasable, electrically programmable read-only-memory (flash EPROM or flash EEPROM) array. In particular, the invention relates to on-chip control of operations such as programming, erasing and compaction of such memories.
Flash EPROMs of the type discussed herein are described in: (a) "A Single Transistor EEPROM cell and its implementation in a 512 K CMOS EEPROM", S. Mukherjee et al., IEDM 1985 (p. 616-619) and in (b) "A 90ns 100 K Erase/Program Cycle Megabit Flash Memory", V. Kynett et al., ISSCC 1989 (p. 140-141). The topic of reference (a) is also discussed in U.S. Pat. No. 4,698,787.
Early flash memories required complex commands from a separate-chip microprocessor when performing write and erase operations. For example, instead of a simple erase command from the microprocessor, the microprocessor was required to furnish such information as the length of the erase pulse and a routine to check for proper erasure. While the commands for write and erase operation could be changed to accommodate manufacturing variations among chips of the same type, those changes had to be programmed by system users, requiring additional system manufacturing time. In addition, replacement of flash memories after exceeding the maximum number or program/erase cycles was made difficult because replacement memories with different characteristics require re-programming of the separate-chip microprocessor, which is often difficult for an end-user.
As flash memory technology evolves, the demand by end users for increasing ease of installation, use and replacement has led to the development of automated control instructions for programming and erasing FLASH memories. The automated program and erase control instructions are embedded in the write state machine (WSM) architecture of such flash EPROMs. The codes for those control instructions are stored in a control-read-only-memory (CROM) in the WSM. With the automated program and erase instructions embedded in the write state machine, the external-to-chip microprocessor need only furnish a simple "erase" command. That is, it is not necessary for the external-to-chip microprocessor to furnish pulse length directions or other information necessary to perform the write and erase operations. The embedded program and erase control instructions allows the memory manufacturer to compensate to alter the program and erase control instructions to compensate for manufacturing variations.
It is not practical to form a microprocessor having all of the features of an external-to-memory-chip microprocessor on a memory chip, which generally has limited space outside of the memory array.
Prior-art implementation of embedded program and erase control instructions generally fall into two groups, random-logic implementation and programmed-logic-array-based implementation (PLA-based implementation).
The first group, random-logic implementations, generally consume a large surface area on a memory chip, such as a flash EPROM chip. Using random-logic implementation, both the program and erase/compaction instructions are generally limited to simple operations because of the required high number of logic gates needed to implement those instructions.
The second group, PLA-based implementations, also generally consume a large chip area. Typically, a separate programmed logic array is dedicated to each mode of operation when used to implement an automated instruction. This requires a minimum of four programmed logic arrays for a flash EPROM chip--one for the control operation, one for the program operation, one for the erase operation, and one for the compaction operation. While more complex instructions can be implemented using this second group rather than the first group, the state density is not high. In addition, instruction changes to compensate for manufacturing variations are generally difficult to make on existing designs.